h8.h
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1
6/*
7 * The contents of this file are subject to the Mozilla Public License
8 * Version 1.0 (the "License"); you may not use this file except in
9 * compliance with the License. You may obtain a copy of the License
10 * at http://www.mozilla.org/MPL/
11 *
12 * Software distributed under the License is distributed on an "AS IS"
13 * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
14 * the License for the specific language governing rights and
15 * limitations under the License.
16 *
17 * The Original Code is legOS code, released October 17, 1999.
18 *
19 * The Initial Developer of the Original Code is Markus L. Noga.
20 * Portions created by Markus L. Noga are Copyright (C) 1999
21 * Markus L. Noga. All Rights Reserved.
22 *
23 * Contributor(s): Markus L. Noga <markus@noga.de>
24 */
25
26#ifndef __sys_h8_h__
27#define __sys_h8_h__
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33// 16 bit timer registers
34//
35
37extern unsigned char T_IER;
38
40extern volatile unsigned char T_CSR;
41
43extern volatile unsigned T_CNT;
44
46extern unsigned T_OCRA;
47
49/* address shared with T_OCRA */
50extern unsigned T_OCRB;
51
53extern unsigned char T_CR;
54
56extern unsigned char T_OCR;
57
58
60extern volatile unsigned T_ICRA;
61
63extern volatile unsigned T_ICRB;
64
66extern volatile unsigned T_ICRC;
67
69extern volatile unsigned T_ICRD;
70
71//
72// TIER bitmasks
73//
74#define TIER_ENABLE_ICA 0x80 // input capture IRQ enables
75#define TIER_ENABLE_ICB 0x40
76#define TIER_ENABLE_ICC 0x20
77#define TIER_ENABLE_ICD 0x10
78#define TIER_ENABLE_OCA 0x08 // output compare IRQ enables
79#define TIER_ENABLE_OCB 0x04
80#define TIER_ENABLE_OF 0x02 // overflow IRQ enable
81#define TIER_RESERVED 0x01 // always set.
82
83//
84// TCSR bitmasks
85//
86#define TCSR_ICA 0x80 // input capture events
87#define TCSR_ICB 0x40
88#define TCSR_ICC 0x20
89#define TCSR_ICD 0x10
90#define TCSR_OCA 0x08 // output compare events
91#define TCSR_OCB 0x04
92#define TCSR_OF 0x02 // overflow event
93#define TCSR_RESET_ON_A 0x01 // reset counter on match A
94
95//
96// TCR bitmasks
97//
98#define TCR_A_RISING 0x80 // input capture on rising
99#define TCR_B_RISING 0x40 // edge. if not set -> lower
100#define TCR_C_RISING 0x20
101#define TCR_D_RISING 0x10
102#define TCR_BUFFER_A 0x08 // buffer A in C
103#define TCR_BUFFER_B 0x04 // buffer B in D
104#define TCR_CLOCK_2 0x00 // clock = pclock / 2
105#define TCR_CLOCK_8 0x01 // clock = pclock / 8
106#define TCR_CLOCK_32 0x02 // clock = pclock / 32
107#define TCR_CLOCK_EXT 0x03 // external clock, rising edge
108
109//
110// TOCR bitmasks
111//
112#define TOCR_OCRA 0x00 // select register to write
113#define TOCR_OCRB 0x10
114#define TOCR_ENABLE_A 0x08 // enable output signals
115#define TOCR_ENABLE_B 0x04
116#define TOCR_HIGH_LEVEL_A 0x02 // set output to high for match
117#define TOCR_HIGH_LEVEL_B 0x01
118
119
120//
121// 8 bit timer registers
122//
123
125extern unsigned char STCR;
126
128extern unsigned char T0_CR;
129
131extern volatile unsigned char T0_CSR;
132
134extern unsigned char T0_CORA;
135
137extern unsigned char T0_CORB;
138
140extern volatile unsigned char T0_CNT;
141
142
144extern unsigned char T1_CR;
145
147extern volatile unsigned char T1_CSR;
148
150extern unsigned char T1_CORA;
151
153extern unsigned char T1_CORB;
154
156extern volatile unsigned char T1_CNT;
157
158
159//
160// CR flag bitmasks
161//
162#define CR_ENABLE_IRQA 0x40
163#define CR_ENABLE_IRQB 0x80
164#define CR_ENABLE_IRQO 0x20
165
166#define CR_CLEAR_NEVER 0x00
167#define CR_CLEAR_ON_A 0x08
168#define CR_CLEAR_ON_B 0x10
169#define CR_CLEAR_ON_EXTERN 0x18
170
171// I don't define speeds here because the STCR bits are involved, too.
172// Also, speeds differ for T0 and T1.
173
174
175//
176// CSR bitmasks
177//
178#define CSR_MATCH_A 0x40
179#define CSR_MATCH_B 0x80
180#define CSR_OVERFLOW 0x20
181
182#define CSR_IGNORE_B 0x00
183#define CSR_0_ON_B 0x04
184#define CSR_1_ON_B 0x08
185#define CSR_TOGGLE_ON_B 0x0c
186
187#define CSR_IGNORE_A 0x00
188#define CSR_0_ON_A 0x01
189#define CSR_1_ON_A 0x02
190#define CSR_TOGGLE_ON_A 0x03
191
192//
193// Serial port
194//
195
197extern volatile unsigned char S_RDR;
198
200extern unsigned char S_TDR;
201
203extern unsigned char S_MR;
204
206extern unsigned char S_CR;
207
209extern volatile unsigned char S_SR;
210
212extern unsigned char S_BRR;
213
215extern unsigned char S_TCR;
216
217//
218// register bitmasks
219//
220#define SMR_SYNC 0x80 // in sync mode, the other settings
221#define SMR_ASYNC 0x00 // have no effect.
222#define SMR_7BIT 0x40
223#define SMR_8BIT 0x00
224#define SMR_P_NONE 0x00
225#define SMR_P_EVEN 0x20
226#define SMR_P_ODD 0x30
227#define SMR_1STOP 0x00
228#define SMR_2STOP 0x08
229#define SMR_MP 0x04 // multiprocessing -> no parity
230 // for mp, mpe in STRC must be set
231#define SMR_CLOCK 0x00 // clock rate for baud rate generator
232#define SMR_CLOCK_4 0x01 // pclock / 4
233#define SMR_CLOCK_16 0x02 // pclock / 16
234#define SMR_CLOCK_64 0x03 // pclock / 64
235
236
237#define SCR_TX_IRQ 0x80 // TIE transmit irq enable
238#define SCR_RX_IRQ 0x40 // RIE receive / recv err irq enable
239#define SCR_TRANSMIT 0x20 // enable transmission
240#define SCR_RECEIVE 0x10 // enable receiving
241#define SCR_MP_IRQ 0x08 // multiprocessing receive irq
242#define SCR_TE_IRQ 0x04 // TEI transmit end irq enable
243#define SCR_INT_CLOCK 0x00 // internal clock source
244#define SCR_EXT_CLOCK 0x02 // external clock source
245#define SCR_CLOCK_OUT 0x01 // output internal clock to SCK pin
246
247
248#define SSR_TRANS_EMPTY 0x80 // transmit buffer empty
249#define SSR_RECV_FULL 0x40 // receive buffer full
250#define SSR_OVERRUN_ERR 0x20 // overrun error
251#define SSR_FRAMING_ERR 0x10 // framing error
252#define SSR_PARITY_ERR 0x08 // parity error
253#define SSR_ERRORS 0x38 // all errors
254#define SSR_TRANS_END 0x04 // transmission end because buffer empty
255#define SSR_MP 0x02 // multiprocessor
256#define SSR_MP_TRANSFER 0x01 // multiprocessor bit transfer
257
258
259//
260// values for the bit rate register BRR
261// assuming CMR_CLOCK selected on 16 MHz processor
262// error <= 0.16%
263//
264
265#define B2400 207
266#define B4800 103
267#define B9600 51
268#define B19200 25
269#define B38400 12
270
271
272// A/D converter
273//
274
276extern volatile unsigned char AD_A_H;
277
279
280extern volatile unsigned char AD_A_L;
281
283extern volatile unsigned char AD_B_H;
284
286
287extern volatile unsigned char AD_B_L;
288
290extern volatile unsigned char AD_C_H;
291
293
294extern volatile unsigned char AD_C_L;
295
297extern volatile unsigned char AD_D_H;
298
300
301extern volatile unsigned char AD_D_L;
302
303
305
306extern volatile unsigned AD_A;
307
309
310extern volatile unsigned AD_B;
311
313
314extern volatile unsigned AD_C;
315
317
318extern volatile unsigned AD_D;
319
320
322extern volatile unsigned char AD_CSR;
323
325extern unsigned char AD_CR;
326
327
328//
329// A/D CSR bitmasks
330//
331
332#define ADCSR_END 0x80
333#define ADCSR_ENABLE_IRQ 0x40
334#define ADCSR_START 0x20
335#define ADCSR_SCAN 0x10 // enable scan mode
336#define ADCSR_TIME_266 0x00 // select A/D conversion time
337#define ADCSR_TIME_134 0x08
338
339#define ADCSR_GROUP_0 0x00 // select scan group
340#define ADCSR_GROUP_1 0x04
341
342#define ADCSR_AN_0 0x00 // first group of inputs to convert
343#define ADCSR_AN_1 0x01
344#define ADCSR_AN_2 0x02
345#define ADCSR_AN_3 0x03 // in scan mode: AN0-AN3
346
347//
348// A/D CR bitmasks
349//
350
351#define ADCR_EXTERN 0x80 // allow external triggering
352
353
354//
355// system control register
356// FIXME: incomplete
357
359extern unsigned char SYSCR;
360
361#define SYSCR_SOFTWARE_STANDBY 0x80 // software standby flag
362
363//
364// I/O ports
365//
366
368extern unsigned char PORT1_PCR;
369
371extern unsigned char PORT2_PCR;
372
374extern unsigned char PORT3_PCR;
375
376
377
379extern unsigned char PORT1_DDR;
380
382extern volatile unsigned char PORT1;
383
384
386extern unsigned char PORT2_DDR;
387
389extern volatile unsigned char PORT2;
390
391
393extern unsigned char PORT3_DDR;
394
396extern volatile unsigned char PORT3;
397
398
400extern unsigned char PORT4_DDR;
401
403extern volatile unsigned char PORT4;
404
405
407extern unsigned char PORT5_DDR;
408
410extern volatile unsigned char PORT5;
411
412
414extern unsigned char PORT6_DDR;
415
417extern volatile unsigned char PORT6;
418
419
421extern volatile unsigned char PORT7;
422
423
424
426extern volatile unsigned int WDT_CSR;
427
428#define WDT_CSR_PASSWORD (0xA500)
429#define WDT_CSR_ENABLE (0x0020)
430#define WDT_CSR_MODE_WATCHDOG (0x0040)
431#define WDT_CSR_MODE_OVERFLOW (0x0000)
432#define WDT_CSR_WATCHDOG_NMI (0x0000)
433#define WDT_CSR_WATCHDOG_RES (0x0008)
434#define WDT_CSR_CLOCK_2 (0x0000)
435#define WDT_CSR_CLOCK_32 (0x0001)
436#define WDT_CSR_CLOCK_64 (0x0002)
437#define WDT_CSR_CLOCK_128 (0x0003)
438#define WDT_CSR_CLOCK_256 (0x0004)
439#define WDT_CSR_CLOCK_512 (0x0005)
440#define WDT_CSR_CLOCK_2048 (0x0006)
441#define WDT_CSR_CLOCK_4096 (0x0007)
442
444extern volatile unsigned char WDT_CNT;
445
446#define WDT_CNT_PASSWORD (0x5A00)
447#define WDT_CNT_CLEAR (0x0000)
448#define WDT_CNT_MSEC_64 (0x0006)
449
450#ifdef __cplusplus
451}
452#endif
453
454#endif // __sys_h8_h__
unsigned char T1_CORB
timer 1 constant B register
unsigned char T1_CORA
timer 1 constant A register
unsigned char PORT4_DDR
port 4 data direction register
volatile unsigned char T_CSR
16-bit timer control / status register
volatile unsigned char T0_CNT
timer 0 counter register
volatile unsigned char PORT7
port 7 input register
volatile unsigned char AD_B_L
A/D converter data register B low.
unsigned T_OCRB
16-bit timer output compare register B
volatile unsigned char WDT_CNT
watch dog timer counter register
volatile unsigned char AD_A_L
A/D converter data register A low.
unsigned char PORT6_DDR
port 6 data direction register
unsigned char S_TCR
serial / timer control register
volatile unsigned T_ICRD
16-bit timer input capture D register
unsigned char PORT3_DDR
port 3 data direction register
unsigned char T_CR
16-bit timer control register
unsigned char T_IER
16-bit timer interrupt enable register
volatile unsigned T_ICRA
16-bit timer input capture A register
volatile unsigned char AD_D_H
A/D converter data register D high.
volatile unsigned char AD_A_H
A/D converter data register A high.
volatile unsigned int WDT_CSR
watch dog timer control register
unsigned char PORT3_PCR
port 3 input pull-up control register
unsigned char PORT1_PCR
port 1 input pull-up control register
volatile unsigned char AD_C_L
A/D converter data register C low.
volatile unsigned T_ICRB
16-bit timer input capture B register
unsigned char S_TDR
serial transmit data register
volatile unsigned AD_A
A/D converter data register A.
volatile unsigned char AD_CSR
A/D converter control / status register.
unsigned char STCR
serial / timer control register
volatile unsigned char AD_D_L
A/D converter data register D low.
unsigned char S_BRR
serial baud rate register
unsigned char PORT2_DDR
port 2 data direction register
unsigned char PORT1_DDR
port 1 data direction register
volatile unsigned char T0_CSR
timer 0 control / status register
volatile unsigned char T1_CNT
timer 1 counter register
unsigned char PORT5_DDR
port 5 data direction register
unsigned char T0_CORA
timer 0 constant A register
volatile unsigned T_CNT
16-bit timer count register
unsigned char S_CR
serial control register
unsigned char PORT2_PCR
port 2 input pull-up control register
unsigned char AD_CR
A/D converter control register.
volatile unsigned char PORT3
port 3 I/O register
volatile unsigned char T1_CSR
timer 1 control / status register
volatile unsigned T_ICRC
16-bit timer input capture C register
unsigned char T0_CR
timer 0 control register
unsigned char SYSCR
system control register
unsigned T_OCRA
16-bit timer output compare register A
volatile unsigned char S_RDR
serial receive data register
volatile unsigned char PORT1
port 1 I/O register
unsigned char T1_CR
timer 1 control register
volatile unsigned AD_B
A/D converter data register B.
volatile unsigned char AD_B_H
A/D converter data register B high.
volatile unsigned char PORT2
port 2 I/O register
volatile unsigned AD_D
A/D converter data register D.
volatile unsigned char S_SR
serial status register
unsigned char S_MR
serial mode register
volatile unsigned char AD_C_H
A/D converter data register C high.
unsigned char T0_CORB
timer 0 constant B register
volatile unsigned char PORT6
port 6 I/O register
volatile unsigned AD_C
A/D converter data register C.
volatile unsigned char PORT5
port 5 I/O register
unsigned char T_OCR
16-bit timer output control register
volatile unsigned char PORT4
port 4 I/O register

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Original code copyright 1998-2005 by the authors.

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